1. Field of the Invention
The present invention relates to a method and apparatus for addressing computer system memory and more particularly to a method and apparatus for extending the memory reference capabilities of a microprocessor.
2. Background Information
The size of the address space available to a given microprocessor is critical in determining whether it can be used in a given application. Address size limits physical memory, and thus the size of an application's data set. Since the limitation is reflected in the width of anything that may contain an address (i.e. program counters, address registers, etc.), it is difficult to increase the effective address space. Therefore, the failure to allocate enough address bits can result in the premature obsolescence of the microprocessor.
The problem of limited addressing is further aggravated in a massively parallel processing system. Massively parallel processing systems use hundreds or thousands of processing elements (PEs) linked together by high speed interconnect networks. Typically, each PE includes a processor, local memory and an interface circuit connecting the PE to the interconnect network. A distributed memory massively parallel processing (MPP) system is one wherein each processor has a favored low latency, high bandwidth path to one or more local memory banks, and a longer latency, lower bandwidth access over the interconnect network to memory banks associated with other processing elements (remote or global memory). In globally addressed distributed memory systems, all memory is directly addressable by any processor in the system. This means that some portion of the address goes to identifying the processor whose memory is being accessed. In an MPP system having 2048 processors eleven bits of addressing go simply to identifying the processor. For a system based on processors having only thirty two bit wide address paths, the loss of the eleven bits limits addressing to a couple of MBytes on each processing node. This is insufficient memory for a high performance MPP system.
One method of extending the address space of address-space-limited microprocessors is segmentation. Under segmentation, an address consists of two parts: a segment number and a segment offset. The segment number is mapped to a physical address and the offset added to that physical address to obtain the physical address of the referenced memory location. The biggest disadvantage has been that, in contrast to paging, segmentation splits the address space into logically separate pieces that must be manipulated as a two-part address. This results in awkwardness (both programmers and compilers must be aware of the address convention) and performance penalties.
There is a similar problem with instruction sets. Commodity microprocessors come with predefined instruction sets. It is difficult to extend the instruction set to create new functionality.
What is needed is a method and system for extending both the address space and the instruction set of commercial microprocessors without the penalties associated with previous solutions.